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RTL Design Engineer

Location: Santa Clara, CA
Posted On: 02/15/2023
Requirement Code: 62763
Requirement Detail

The Memory PHY RTL team is looking for passionate and experienced Design Engineers for RTL Design and development of high speed Memory PHY IPs.


RESPONSIBILITIES:
• Digital design and RTL coding.
• Digital design of behavioral analog mix signal sub component using System Verilog and other languages.
• Verification tasks including clock, voltage, and reset domain crossing checks, LEC, and review/debug of other verification checks • RTL debug and support (Verdie experience preferred) • Scripting (Python, Perl, CSH, TCL) • Co-ordinating design verification and implementation activities.


REQUIREMENTS
• RTL coding experience in Verilog/System Verilog • Experience of GDDR/DDR/Serdes PHY • Experience of RTL design checks including CDC, VDC, RDC, gate and RTL timing simulation, power simulation • Ability to write and debug scripts in C, Perl, Python, etc.
• Ability to plan and work independently


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