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Validation Engineer

Location: Austin, TX
Posted On: 02/15/2023
Requirement Code: 62756
Requirement Detail

Technical, hands-on engineer responsible for Datacenter Server SoC Post-Silicon high speed IO features validation and enablement at the silicon SoC level up through BIOS, system firmware, and OS levels on AMD Server products. This individual will be primarily working with AMD validation engineers in test execution, troubleshooting failures, platform setup and construction.
• Execute feature enablement and validation test plans for High Speed IO such as PCIe, CXL, USB for SoC- and system-level SoC features across all AMD Server products.
• Develop post-silicon validation infrastructure (software, hardware, automation environment, and lab setup)
• Debug and drive root-cause analysis for SoC related issues
• Collaborate with cross-functional teams in developing tools to improve SoC validation and debug
• Perform misc. lab work including CPU part socketing, PCIe/Card/riser-board insertion and minor board rework
• Perform data collection using test equipment such as high speed oscilloscope and protocol analyzer
• Report test progress and document failure analysis
• Experience with PC architecture
• Prior experience in one or more of the following high speed IO technologies: PCIe, CXL, USB, SATA.
• Familiar with using server OS such as Windows Server, Ubuntu, RedHat.
• Familiar with navigating and configuring system via BIOS.
• Good at debugging issues
• Familiarity with programming / scripting language (C/C , Python, Perl, ...)
• Must be a self-starting team player with excellent communication skills who can work with minimal guidance
• Strong verbal and written English communication skills
Minimum Required Qualifications
• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science or other technical degree OR
• Associate Degree in above mentioned areas with 5 years of working experience in design, verification or validation
• Understanding of modern x86 microprocessor architecture and Server platform architecture is highly desired
• Knowledge on PCIe and CXL protocol is a plus

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